An etched silicon wafer

Intel's silicon wafer

A wafer is a thin slice of semiconductor material, such as a silicon crystal, used in the fabrication of integrated circuits and other microdevices. The wafer serves as the substrate for microelectronic devices built in and over the wafer and undergoes many microfabrication process steps such as doping or ion implantation, etching, deposition of various materials, and photolithographic patterning.

Several types of solar cells are made from such wafers. A solar wafer is a circular solar cell made from the entire wafer (rather than cutting into smaller rectangular solar cells).

[edit] Formation

The Czochralski process.

2 inch, 4 inch, 6 inch, and 8 inch wafers

Wafers are formed of highly pure (99.9999% purity), ^[1] nearly defect-free single crystalline material^[2]. One process for forming crystalline wafers is known as Czochralski growth invented by the Polish chemist Jan Czochralski. In this process, a cylindrical ingot of high purity crystalline silicon is formed by pulling a seed crystal from a 'melt'. ^{[3] [4]}

The ingot is then sliced with an inner diameter diamond-coated blade and polished to form wafers ^[5]. The size of wafers for photovoltaics is 100 – 200 mm square and the thickness is 200 - 300 μm. In the future, 160 μm will be the standard ^[6]. Electronics use wafer sizes from 100 - 300mm diameter.

The resulting thin wafers can then be doped to achieve the desired electronic properties.

[edit] Cleaning, texturing and etching

Wafers are cleaned with weak acids to remove unwanted particles, or repair damage caused during the sawing process. When used for solar cells, the wafers are textured to create a rough surface to increase their efficiency. The generated PSG (phosphorus silicate glass) is removed from the edge of the wafer in the etching ^[7].

[edit] Wafer properties

[edit] Standard wafer sizes

Silicon wafers are available in a variety of sizes from 25.4 mm (1 inch) to 300 mm (11.8 inches).^[8] Semiconductor fabrication plants (also known as fabs) are defined by the size of wafers that they are tooled to produce. The size has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab considered to be 300mm (12 inch), with the next standard projected to be 450mm (18 inch).^[9][10] Intel, TSMC and Samsung are separately conducting research to the advent of 450mm "prototype" (research) fabs by 2012, though serious hurdles remain. Dean Freeman, an analyst with Gartner Inc., predicted that production fabs could emerge sometime between the 2017 and 2019 timeframe,^[11] a lot of that will depend on a plethora of new technological breakthroughs and not simply "extending" current technology.

• 1 inch.
• 2 inch (50.8 mm). Thickness 275 µm.
• 3 inch (76.2 mm). Thickness 375 µm.
• 4 inch (100 mm). Thickness 525 µm.
• 5 inch (127 mm) or 125 mm (4.9 inch). Thickness 625 µm.
• 150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
• 200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
• 300 mm (11.8 inch, usually referred to as "12 inch" or "Pizza size" wafer). Thickness 775 µm.
• 450 mm ("18 inch"). Thickness 925 µm (expected).^[12]

Wafers grown using materials other than silicon are generally not available in sizes over 100 mm, and will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the mechanical strength of the material used; the wafer must be thick enough to support its own weight without cracking during handling.

With larger wafers, less marginal space remains on the edges as a percentage of total space and can significantly increase the yield per wafer. This is the basis of shifting to larger and larger wafer sizes. Conversion to 300 mm wafers from 200 mm wafers began in earnest in 2000, and reduced the price per die about 30-40%.^[13] However, this was not without significant problems for the industry.

The next step to 450 mm should accomplish similar productivity gains as the previous size increase. However, machinery needed to handle and process larger wafers results in increased investment costs to build a single factory. There is considerable resistance to moving up to 450 mm by 2012 despite the obvious productivity enhancements, mainly because companies feel it would take too long to recoup their investment.^[14] The difficult and costly 300 mm process only accounted for appoximately 20% of worldwide capacity on a square inches basis by the end of 2005.^[15] The step up to 300 mm required a major change from the past, with fully automated factories using 300 mm wafers versus barely automated factories for the 200 mm wafers. These major investments were undertaken in the economic downturn following the dot-com bubble, resulting in huge resistance to upgrading to 450 mm by the original timeframe.

Other initial technical problems in the ramp up to 300 mm included vibrational effects, gravitational bending (sag), and problems with flatness. Among the new problems in the ramp up to 450 mm are that the crystal ingots will be 3 times heavier (total weight a metric ton) and take 2-4 times longer to cool, and the process time will be double.^[16] All told, the development of 450 mm wafers require significant engineering, time, and cost to overcome.

[edit] Analytical die count estimation

For any given wafer diameter [d, mm] and target IC size [S, mm²], there is an exact number of integral die pieces that can be sliced out of the wafer. The gross Die Per Wafer [DPW] can be estimated by the following expression:

Note, that the gross die count does not take into account the die defect loss, various alignment markings and test sites on the wafer.

[edit] Crystalline orientation

Diamond Cubic Crystal Structure, Silicon unit cell

Flats can be used to denote doping and crystallographic orientation. Red represents material that has been removed.

Wafers are grown from crystal having a regular crystal structure, with silicon having a diamond cubic structure with a lattice spacing of 5.430710 Å (0.5430710 nm).^[17] When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the Miller index with [100] or [111] faces being the most common for silicon.^[17] Orientation is important since many of a single crystal's structural and electronic properties are highly anisotropic. Ion implantation depths depend on the wafer's crystal orientation, since each direction offers distinct paths for transport. ^[18] Wafer cleavage typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("dies") so that the billions of individual circuit elements on an average wafer can be separated into many individual circuits.

[edit] Wafer flats and orientation notches

Wafers under 200 mm generally have flats cut into one or more sides indicating crystallographic planes of high symmetry (usually the {110} face) and, in old-fashioned wafers (those below about 100 mm diameter), the wafer's orientation and doping type (see illustration for conventions). Modern wafers use a notch to convey this information, in order to waste less material ^[19].

[edit] Impurity doping

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity doping concentration between 10¹³ and 10¹⁶ per cm³ of boron, phosphorus, arsenic, or antimony which is added to the melt and defines the wafer as either bulk n-type or p-type.^[20] However, compared with single-crystal silicon's atomic density of 5×10²² atoms per cm³, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some interstitial oxygen concentration. Carbon and metallic contamination are kept to a minimum.^[21] Transition metals, in particular, must be kept below parts per billion concentrations for electronic applications.^[22]

[edit] Compound semiconductors

While silicon is the most prevalent type of wafer used in the electronics industry, other compound III-V or II-VI type wafers have also been employed. Gallium arsenide (GaAs) wafers are one common III-V semiconductor material which can be produced using the Czochralski process.^[4]

[edit] See also

• Crystalline silicon
• Epilayer
• Epitaxy
• Junction
• Layer (electronics)
• Low-cost solar cell
• Rapid thermal processing
• Refining
• Screen printing
• Silicon on insulator (SOI) wafers
• Solar panel
• RCA clean
• Zone melting

[edit] References

12

[edit] External links

Wikimedia Commons has media related to: Wafers

• Everything Wafers - A guide to semiconductor substrates type, property, cleaving, etching, and fabrication.
• Star Silicon - Information and products related to the Silicon Wafer and Solar Wafer industry.