POWER7

Designed by	IBM
Min. feature size	45 nm
Instruction set	IBM POWER
Cores	4, 6, 8
L3 cache	32 mb

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Historical
POWER • POWER1 • POWER2 • POWER3 • POWER4 • PowerPC-AS • PPC6xx • Gekko • AIM alliance
Current
PowerPC • e200 • e300 • e500 • e600 • QorIQ • PA6T • POWER5 • POWER6 • PPC4xx • PowerPC 7xx • 7xxx • PPC970 • Cell • Xenon • Broadway • Titan
Future
POWER7 • e700
Related Links
RISC • System p • System i • Blue Gene • Power.org • PAPR • PReP • CHRP • more...

POWER7 is a microprocessor currently under development at about a dozen IBM sites including IBM's Rochester, Austin and Böblingen laboratories as of April 2006^[update]. The POWER7 is the successor to POWER6 and will be released in mid-2010.^[1][2]

Contents 1 Deployment 2 History 3 Specifications 4 See also 5 References 6 External links

[edit] Deployment

IBM will release POWER7 based Power Systems in 2010 and will also be available as upgrades to Power 570 and 595 systems. POWER7 will come in four, six or eight core versions.^[3]

[edit] History

IBM won a $244 million DARPA contract in November 2006 to develop a petascale supercomputer architecture before the end of 2010 in the HPCS project. The contract also states that the architecture shall be available commercially. IBM's proposal, PERCS (Productive, Easy-to-use, Reliable Computer System), which won them the contract, is based on the POWER7 processor, AIX operating system and General Parallel File System.^[4]

One feature that IBM and DARPA collaborated on is modifying the addressing and page table hardware to support global shared memory space for POWER7 clusters. This enables research scientists to program a cluster as if it were a single system, without using message passing. From a productivity standpoint, this is essential since most scientists are not conversant with MPI or other exotic parallel programming techniques used in clusters.^[5]

Although it has been suggested that POWER7 and future AMD Opteron processors will share CPU socket layout, that convergence has never been confirmed by either IBM or AMD.^[6][7]

[edit] Specifications

POWER7 will have these specifications:^[8][9]

• 45 nm process, 567mm²
• 4.04 GHz clock speed
• max 2 chips per multi chip module
  • 4, 6 or 8 cores per chip
    • 4 SMT threads per core
    • 12 execution units per core:
      • 2 fixed-point units
      • 2 load/store units
      • 4 double-precision floating-point units
      • 1 vector unit supporting VSX
      • 1 decimal floating-point unit
      • 1 branch unit
      • 1 condition register unit
  • 32 MB on-die L3 cache, shared by all cores. The cache is implemented in eDRAM, which doesnt requirer as many transistor per cell as a standard (SRAM)^[5] so it allows for a larger cache yet while using the same area as SRAM.

This gives the following theoretical performance figures:

• max 517.1 GFLOPS per module
  • max 258.6 GFLOPS per chip
    • max 32.3 GFLOPS per core

[edit] See also

• Power Architecture
• IBM POWER
• POWER6
• Blue Waters

[edit] References

[edit] External links

• IBM DeveloperWorks
• IBM Won DARPA HPCS Phase-III
• IBM Won DARPA HPCS Phase-II
• IBM PERCS