Double Data Rate synchronous dynamic random access memory (or also known as DDR SDRAM) is a class of memory integrated circuits used in computers. It achieves nearly twice the bandwidth of the preceding single data rate (SDR) SDRAM by double pumping (transferring data on the rising and falling edges of the clock signal) without increasing the clock frequency.

With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) x 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s.

"Beginning in 1996 and concluding in June 2000, JEDEC developed the DDR (Double Data Rate) SDRAM specification (JESD79)."^[1] JEDEC has set standards for data rates of DDR SDRAM, divided into two parts. The first specification is for memory chips, and the second is for memory modules. As DDR SDRAM is superseded by the newer DDR2 SDRAM, the older DDR version is sometimes referred to as DDR1 SDRAM.

Contents 1 Specification standards 1.1 Chips and modules 1.2 Chip characteristics 1.3 Module characteristics 1.4 History 1.4.1 Double data rate (DDR) SDRAM specification 2 High density vs low density 2.1 Organization 2.2 High density RAM 3 Alternatives 4 MDDR 5 References 6 See also 7 External links

[edit] Specification standards

[edit] Chips and modules

Standard name	Memory clock (MHz)	Cycle time[2] (ns)	I/O bus clock (MHz)	Data transfer rate (MHz)	JEDEC standard VDDQ voltage (V)	Module name	Peak transfer rate (MB/s)
DDR-200	100	10	100	200	2.5±0.2	PC-1600	1600
DDR-266	133	7.5	133	266	2.5±0.2	PC-2100	2100
DDR-333	166	6	166	333	2.5±0.2	PC-2700	2700
DDR-400	200	5	200	400	2.6±0.1	PC-3200	3200

Note: All above listed are specified by JEDEC as JESD79.^[3] All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips.

The package sizes in which DDR SDRAM is manufactured are also standardized by JEDEC.

There is no architectural difference between DDR SDRAM designed for different clock frequencies, for example, PC-1600, designed to run at 100 MHz, and PC-2100, designed to run at 133 MHz. The number simply designates the data rate at which the chip is guaranteed to perform, hence DDR SDRAM is guaranteed to run at lower and can possibly run at higher clock rates than those for which it was made.^[4] These practices are known as underclocking and overclocking respectively.

DDR SDRAM for desktop computers, DIMMs, have 184 pins (as opposed to 168 pins on SDRAM, or 240 pins on DDR2 SDRAM), and can be differentiated from SDRAM DIMMs by the number of notches (DDR SDRAM has one, SDRAM has two). DDR SDRAM for notebook computers, SO-DIMMs, have 200 pins, which is the same number of pins as DDR2 SO-DIMMs. These two specifications are notched very similarly and care must be taken during insertion when you are unsure of a correct match. DDR SDRAM operates at a voltage of 2.5 V, compared to 3.3 V for SDRAM. This can significantly reduce power consumption. Chips and modules with DDR-400/PC-3200 standard have a nominal voltage of 2.6 V.

Many new chipsets use these memory types in dual-channel configurations, which doubles or quadruples the effective bandwidth.

[edit] Chip characteristics

DRAM density

Size of the chip in megabits. For example, 256 Mibit, or 32 MiB chip. Nearly all motherboards only recognize 1 GiB modules if they are low density 64M×8 modules. If high density 128M×4 1 GiB modules are used, they most likely will not work. The JEDEC standard allows 128M×4 only for slower buffered/registered modules designed specifically for some servers, but some generic manufacturers do not comply.^[5]

DRAM organization

Written in the form of 64M×4, where 64M is a number of storage units (64 million), x4 (pronounced "by 4") — number of bits per chip, which equals the number of bits per storage unit. There are ×4, ×8, and ×16 DDR chips. The ×4 chips allow the use of advanced error correction features like Chipkill, memory scrubbing and Intel SDDC, while the ×8 and ×16 chips are somewhat more expensive.

[edit] Module characteristics

Capacity

No of DRAM Devices

The number of chips is a multiple of 8 for non-ECC modules and a multiple of 9 for ECC modules. Chips can occupy one side (single sided) or both sides (dual sided) of the module. The maximum number of chips per DDR module is 36 (9×4).

No of DRAM Ranks

(also known as rows or sides) Any given module can have 1, 2, or 4 ranks, but only 1 rank of a module can be active at any moment in time. When a module has two or more ranks, the memory controller must periodically switch between them by performing close and open operations. Do not confuse rows in this context with rows used to describe internal chip architecture (that is why the term rank is to be preferred). The term sides is also confusing because it incorrectly suggests that this is tied to the physical placement of chips on the module.

Timings: CAS latency (CL), clock cycle time (t_CK), row cycle time (t_RC), refresh row cycle time (t_RFC), row active time (_tRAS).

Buffering

Registered vs unbuffered

Packaging

Typically DIMM or SO-DIMM

Power consumption

Increases with clock rate.^[6]

Module and chip characteristics are inherently linked.

Total module capacity is a product of one chip's capacity by the number of chips. ECC modules multiply it by 8/9 because they use one bit per byte for error correction. A module of any particular size can therefore be assembled either from 32 small chips (36 for ECC memory), or 16(18) or 8(9) bigger ones.

DDR memory bus width per channel is 64 bits (72 for ECC memory). Total module bit width is a product of bits per chip by number of chips. It also equals number of ranks (rows) multiplied by DDR memory bus width. Consequently a module with greater amount of chips or using ×8 chips instead of ×4 will have more ranks.

Example: Variations of 1 GiB PC2100 Registered DDR SDRAM module with ECC

Module size (GiB)	Number of chips	Chip size (Mbit)	Chip organization	Number of rows (ranks)
1	36	256	64M×4	2
1	18	512	64M×8	2
1	18	512	128M×4	1

This example compares different real-world server memory modules with a common size of 1 GiB. One should definitely be careful buying 1 GiB memory modules, because all these variations can be sold under one price position without stating whether they are ×4 or ×8, single or dual ranked.

There is a common belief that number of module ranks or rows equals number of sides. As above data shows, this is not true. One can find 2-side/1-rank or 2-side/4-rank modules. One can even think of a 1-side/2-rank memory module having 16(18) chips on single side ×8 each, but it's unlikely such a module was ever produced.

[edit] History

[edit] Double data rate (DDR) SDRAM specification

From JEDEC Board Ballot JCB-99-70, and modified by numerous other Board Ballots, formulated under the cognizance of Committee JC-42.3 on DRAM Parametrics.

Standard No. 79 Revision Log:

• Release 1, June 2000
• Release 2, May 2002
• Release C, March 2003 - JEDEC Standard No. 79C.^[7]

"This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well."

[edit] High density vs low density

High density memory here means non-ECC 184 pin SDRAM memory.

[edit] Organization

PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. As the memory is double pumped, this means that the effective clock rate of PC3200 memory is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with sixteen 512 Mbit chips, 8 down each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized with 64 Mbits and a data width of 8 bits for each chip, commonly expressed as 64M×8. Memory manufactured in this way is low density RAM and will usually be compatible with any motherboard specifying PC3200 DDR-400 memory.

[edit] High density RAM

In the context of the 1 GB non-ECC PC3200 SDRAM module, there is very little visually to differentiate low density from high density RAM. High density DDR RAM modules will, like their low density counterparts, usually be double-sided with eight 512 Mbit chips per side. The difference is that each chip, instead of being organized in a 64M×8 configuration is organized with 128 Mbits and a data width of 4 bits, or 128M×4. To further confuse the issue, some RAM is labeled as 128M×8, and is also called high density.

Most high density PC3200 modules are assembled using Samsung chips. These chips come in both the familiar 22 × 10 mm (approx.) TSOP2 and smaller squarer 12 × 9 mm (approx.) FBGA package sizes. High density Samsung chips can be identified by the numbers on each chip. If the sixth and seventh characters are 04 (for example K4H510438D-UCCC) then the chips are ×4 and high density. If the sixth and seventh characters are 08 then the chips are ×8 and low density.

High density RAM devices were designed to be used in registered memory modules for servers. As a result, performance or response times may suffer when used on a desktop or workstation. JEDEC standards do not apply to high-density DDR RAM in desktop implementations. JEDEC's technical documentation, however, supports 128M×4 semiconductors as such that contradicts 128×4 being classified as high density. As such, high density is a relative term, which can be used to describe memory which is not supported by a particular motherboard's memory controller.

[edit] Alternatives

DDR SDRAM Standard	Frequency (MHz)	Voltage[8]
DDR	100-200	2.5/2.6
DDR2	200-533	1.8
DDR3	400-800	1.5

DDR (DDR1) has been superseded by DDR2 SDRAM, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR2 are Rambus XDR DRAM. DDR2 has become the standard, as XDR is lacking support. DDR3 SDRAM is a new standard that offers even higher performance and new features.

DDR's prefetch buffer depth is 2 bits, while DDR2 uses 4 bits. Although the effective clock rates of DDR2 are higher than for DDR, the overall performance was no greater in the early implementations, primarily due to the high latencies of the first DDR2 modules. DDR2 started to be effective by the end of 2004, as modules with lower latencies became available.^[9]

Memory manufacturers have stated that it is impractical to mass-produce DDR1 memory with effective clock rates in excess of 400 MHz. DDR2 picks up where DDR1 leaves off, and is available at clock rates of 400 MHz and higher. RDRAM is a particularly expensive alternative to DDR SDRAM, and most manufacturers have dropped its support from their chipsets. DDR1 memory's prices have substantially increased since Q2 2008 while DDR2 prices are reaching an all-time low. In January 2009, 1 GB DDR1 is 2-3 times more expensive than 1 GB DDR2. High density DDR RAM will suit about 10% of PC motherboards on the market while low density will suit almost all motherboards on the PC Desktop market.

[edit] MDDR

MDDR is an acronym that some enterprises use for Mobile DDR SDRAM, a type of memory used in some portable electronic devices, like mobile phones, handhelds, and digital audio players. While standard DDR SDRAM operates at a voltage of 2.5 V, MDDR operates at voltage of 1.8 V, which allows a reduced power consumption.

[edit] References

[edit] See also

• Serial presence detect
• Fully buffered DIMM
• List of device bandwidths

[edit] External links

• Official JEDEC website

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